Status
Live
9 units live.
SoC and family
Arm
Device type
juno
Activity
First seen 1 Nov 2025, last seen 6 Nov 2026.
Data as of 6 Nov 2026, 18:21 UTCLast synced:LAVA 6 Nov 2026, 18:21 UTCJenkins 6 Nov 2026, 18:33 UTCS3 export 7 Oct 2026, 09:53 UTC
Evaluations
13,16013,239 attempts, 96 cancelled
Completion
99.0%of 13,143 attemptsComplete out of complete and incomplete attempts. Cancelled attempts are listed, never counted.
Evaluated pass rate
99.9%of 13,004 evaluations with a verdictFinal attempts that passed, out of pass and code. Lab 0, cancelled 96 and unclassified 60 are shown, never folded in.
Failed after retries
62 of 13,16079 failed first time, 16 passed on retry
Changes with a failed boot on this board
0 of 142Allow-CI+2 for TF-A; linked TF-M runs. 2 with no boot verdict. Linked to a change: 47.7% of 13,167 evaluations

Last 30 days

Evaluations per day, stacked by final outcome.

Test-case detail: 8 Oct 2026 to 6 Nov 2026
Test-case detail: 8 Oct 2026 to 6 Nov 2026. 0 days without data.

History by month

Before the live window we know whether each attempt completed and how retries ended, not why it failed or which change it was. Months with no data held are listed under the chart.

  • Evaluations per month
  • Incomplete attempts, % of attempts
  • Failed after retries, % of evaluations
Incidents marked: Lab 17 Sep, Lab 1 Feb.
Test-case detail: September 2026 to November 2026.
Job level only: 1 Nov 2025 to 27 Feb 2026No data held: 28 Feb 2026 to 28 Feb 2026Job level only: 1 Mar 2026 to 6 Sep 2026Test-case detail: 7 Sep 2026 to 30 Sep 2026Test-case detail: 1 Oct 2026 to 6 Nov 2026
Job-level history: 1 Nov 2025 to 6 Sep 2026. Test-case detail: 7 Sep 2026 to 6 Nov 2026. 1 day without data.

Units

CI attempts per physical unit, retries included. Passing on another unit can help identify a unit fault. Health checks are fleet health.

Unit
Attempts
First-attempt failures
Passed on another unit
Passed on the same unit
Last health check
1,516
15
8
1
Complete 6 Nov 01:10
1,546
11
2
0
Complete 6 Nov 01:12
1,456
11
1
0
Complete 6 Nov 01:27
1,359
9
0
0
Complete 6 Nov 01:08
1,532
9
1
0
Complete 6 Nov 01:41
1,343
8
1
0
Complete 6 Nov 01:13
1,553
7
1
0
Complete 6 Nov 13:49
1,384
5
0
0
Complete 6 Nov 01:21
1,461
4
1
0
Complete 6 Nov 01:46

Evaluations

One row per builder build on this board, newest first, with every attempt. CI runs only; 50 of 1,514 shown.

When
Build
Change
Branch
Attempts
Verdict
6 Nov 18:18
feat(lfa): prevent LFA when not allowed by RMM
integration
built refs/changes/33/52533/5
Running
6 Nov 18:18
feat(lfa): prevent LFA when not allowed by RMM
integration
built refs/changes/33/52533/5
Pass
6 Nov 14:09
fix(tc): increase BL2 memory allocation
integration
built refs/changes/31/56231/2
Pass
6 Nov 14:03
fix(tc): increase BL2 memory allocation
integration
built refs/changes/31/56231/2
Pass
6 Nov 13:57
fix(tc): increase BL2 memory allocation
integration
built refs/changes/31/56231/2
Pass
6 Nov 13:50
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 13:44
fix(tc): increase BL2 memory allocation
integration
built refs/changes/31/56231/2
Pass
6 Nov 13:40
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 13:36
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 13:32
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 13:27
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 12:23
feat(cpus): introduce a framework for IMP_DEF EL3 trap handling
integration
built refs/changes/68/41668/9
Pass
6 Nov 12:18
refactor(allwinner): count the cores a SoC really has
integration
built refs/changes/98/55198/4
Pass
6 Nov 12:13
refactor(allwinner): count the cores a SoC really has
integration
built refs/changes/98/55198/4
Pass
6 Nov 12:08
refactor(allwinner): count the cores a SoC really has
integration
built refs/changes/98/55198/4
Pass
6 Nov 12:02
feat(cpus): introduce a framework for IMP_DEF EL3 trap handling
integration
built refs/changes/68/41668/9
Pass
6 Nov 11:57
feat(cpus): introduce a framework for IMP_DEF EL3 trap handling
integration
built refs/changes/68/41668/9
Pass
6 Nov 11:51
refactor(allwinner): count the cores a SoC really has
integration
built refs/changes/98/55198/4
Pass
6 Nov 11:46
feat(cpus): introduce a framework for IMP_DEF EL3 trap handling
integration
built refs/changes/68/41668/9
Pass
6 Nov 11:41
refactor(allwinner): count the cores a SoC really has
integration
built refs/changes/98/55198/4
Pass
6 Nov 11:37
feat(fvp): Add smmu_info fields and configure interrupt as MSI
integration
built refs/changes/46/51846/9
Pass
6 Nov 11:33
fix(psci): run the arch setup before pwr_domain_on_finish()
integration
built refs/changes/88/55088/5
Pass
6 Nov 11:26
docs(maintainers): add maintainer entry for QTI PMIC driver
integration
built refs/changes/40/56040/4
Pass
6 Nov 11:21
feat(fvp): Add smmu_info fields and configure interrupt as MSI
integration
built refs/changes/46/51846/9
Pass
6 Nov 11:15
docs(maintainers): add maintainer entry for QTI PMIC driver
integration
built refs/changes/40/56040/4
Pass
6 Nov 11:10
docs(maintainers): add maintainer entry for QTI PMIC driver
integration
built refs/changes/40/56040/4
Pass
6 Nov 11:03
feat(fvp): Add smmu_info fields and configure interrupt as MSI
integration
built refs/changes/46/51846/9
Pass
6 Nov 10:58
docs(maintainers): add maintainer entry for QTI PMIC driver
integration
built refs/changes/40/56040/4
Pass
6 Nov 10:52
feat(fvp): Add smmu_info fields and configure interrupt as MSI
integration
built refs/changes/46/51846/9
Pass
6 Nov 10:46
docs(maintainers): add maintainer entry for QTI PMIC driver
integration
built refs/changes/40/56040/4
Pass
6 Nov 10:39
feat(fvp): Add smmu_info fields and configure interrupt as MSI
integration
built refs/changes/46/51846/9
Pass
6 Nov 10:34
fix(psci): run the arch setup before pwr_domain_on_finish()
integration
built refs/changes/88/55088/5
Pass
6 Nov 10:20
refactor(cpus): normalize Cortex-A78AE header macro names
integration
built refs/changes/46/56146/4
Pass
6 Nov 10:15
refactor(cpus): normalize Cortex-A78AE header macro names
integration
built refs/changes/46/56146/4
Pass
6 Nov 10:06
refactor(cpus): normalize Cortex-A78AE header macro names
integration
built refs/changes/46/56146/4
Pass
6 Nov 09:58
refactor(cpus): normalize Cortex-A78AE header macro names
integration
built refs/changes/46/56146/4
Pass
6 Nov 09:43
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 09:38
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 09:33
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 09:26
fix(cpus): add erratum 4060225 for Neoverse-V3AE
lts-v2.10
built refs/changes/25/56225/1
Pass
6 Nov 09:20
fix(psci): update req pwr states after validate
integration
built refs/changes/26/56226/1
Pass
6 Nov 09:17
fix(psci): update req pwr states after validate
integration
built refs/changes/26/56226/1
Pass
6 Nov 09:11
fix(psci): update req pwr states after validate
integration
built refs/changes/26/56226/1
Pass
6 Nov 09:07
fix(psci): update req pwr states after validate
integration
built refs/changes/26/56226/1
Pass
6 Nov 09:02
feat(cpus): introduce a framework for IMP_DEF EL3 trap handling
integration
built refs/changes/68/41668/8
Pass
6 Nov 08:57
refactor(cpus): integrate ERRATA_NON_ARM_INTERCONNECT errata into the generic framework
integration
built refs/changes/29/56029/2
Pass
6 Nov 08:51
refactor(cpus): integrate ERRATA_NON_ARM_INTERCONNECT errata into the generic framework
integration
built refs/changes/29/56029/2
Pass
6 Nov 08:46
refactor(cpus): integrate ERRATA_NON_ARM_INTERCONNECT errata into the generic framework
integration
built refs/changes/29/56029/2
Pass
6 Nov 08:41
feat(cpus): introduce a framework for IMP_DEF EL3 trap handling
integration
built refs/changes/68/41668/8
Pass
6 Nov 08:37
feat(cpus): introduce a framework for IMP_DEF EL3 trap handling
integration
built refs/changes/68/41668/8
Pass

Fleet health

Health checks, not CI results. They never count towards any rate on this page.

0 of 63 health checks failed in the last 7 days.
All passed
Showing the latest 63 checks.
One tick per health check, oldest to newest. Each opens its job.PassedFailedCancelled

Incidents

  1. Lab 1 Feb 2026 to 28 Feb 2026

    not recorded

  2. Lab 17 Sep 2026 to 18 Sep 2026

    LAVA logger DNS failures